General-purpose timers (TIM15/16/17) RM0091
426/742 Doc ID 018940 Rev 1
18.6.5 TIM16 and TIM17 event generation register (TIM16_EGR and
TIM17_EGR)
Address offset: 0x14
Reset value: 0x0000
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow regarding the repetition counter value (update if repetition counter = 0)
and if the UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if
URS=0 and UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by a trigger event (refer to Section 18.5.3: TIM15 slave
mode control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1
register.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. BG TG COMG Res. Res. Res. CC1G UG
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Bits 15:8 Reserved, always read as 0.
Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled.
Bit 5 COMG: Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels that have a complementary output.
Bits 4:2 Reserved, always read as 0.
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