General-purpose timers (TIM2 and TIM3) RM0091
346/742 Doc ID 018940 Rev 1
16.4.13 TIM2 and TIM3 capture/compare register 1 (TIM2_CCR1 and
TIM3_CCR1)
Address offset: 0x34
Reset value: 0x00000000
16.4.14 TIM2 and TIM3 capture/compare register 2 (TIM2_CCR2 and
TIM3_CCR2)
Address offset: 0x38
Reset value: 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1[31:16] (TIM2 only)
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
CCR1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2).
Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Otherwise the preload value is copied in the active capture/compare 1 register
when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2[31:16] (TIM2 only)
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
CCR2[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
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