STMicroelectronics STM32F05 series - Figure 106. Counter Timing Diagram, Internal Clock Divided by 2; Figure 107. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0 X36; Figure 108. Counter Timing Diagram, Internal Clock Divided by N

General-purpose timers (TIM2 and TIM3) RM0091
302/742 Doc ID 018940 Rev 1
Figure 106. Counter timing diagram, internal clock divided by 2
Figure 107. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 108. Counter timing diagram, internal clock divided by N
0002 0000 0001 0002 0003
CNT_EN
TImer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0003
0001
Counter underflow
Update event (UEV)
CK_INT
CK_INT
0036 0035
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0034
0035
Counter overflow (cnt_ovf)
Update event (UEV)
Timer clock = CK_CNT
Counter register
00
20
1F
Update interrupt flag (UIF)
Counter underflow
Update event (UEV)
CK_INT
01