RM0091 Inter-integrated circuit (I
2
C) interface
Doc ID 018940 Rev 1 477/742
23.4.7 Data transfer
The data transfer is managed through transmit and receive data registers and a shift
register.
Reception
The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is
received), the shift register is copied into I2Cx_RXDR register if it is empty (RXNE=0). If
RXNE=1, meaning that the previous received data byte has not yet been read, the SCL line
is stretched low until I2Cx_RXDR is read. The stretch is inserted between the 8th and 9th
SCL pulse (before the Acknowledge pulse).
Figure 200. Data reception
Transmission
If the I2Cx_TXDR register is not empty (TXE=0), its content is copied into the shift register
after the 9th SCL pulse (the Acknowledge pulse). Then the shift register content is shifted
out on SDA line. If TXE=1, meaning that no data is written yet in I2Cx_TXDR, SCL line is
stretched low until I2Cx_TXDR is written. The stretch is done after the 9th SCL pulse.
xx
Shift register
data1
data1
xx data2
RXNE
ACK pulse
data0 data2
ACK pulse
xx
I2C_RXDR
rd data1rd data0
SCL
legend:
SCL
stretch
MS19848V1
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