RM0091 Power control (PWR)
Doc ID 018940 Rev 1 75/742
Entering Standby mode
Refer to Ta bl e 1 7 for more details on how to enter Standby mode.
In Standby mode, the following features can be selected by programming individual control
bits:
● Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 21.3: IWDG functional description in Section 21: Independent watchdog
(IWDG).
● real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control
register (RCC_BDCR)
● Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
● External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup
domain control register (RCC_BDCR)
Exiting Standby mode
The microcontroller exits the Standby mode when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the enabled WKUPx pins or the rising edge of an RTC alarm
occurs (see Figure 227: RTC block diagram). All registers are reset after wakeup from
Standby except for Power control/status register (PWR_CSR).
After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.). The SBF status
flag in the Power control/status register (PWR_CSR) indicates that the MCU was in Standby
mode.
Refer to Ta bl e 1 7 for more details on how to exit Standby mode.
I/O states in Standby mode
In Standby mode, all I/O pins are high impedance except:
● Reset pad (still available)
● PC13, PC14 and PC15 if configured by RTC or LSE
● WKUPx pins
Table 17. Standby mode
Standby mode Description
Mode entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– Set SLEEPDEEP in Cortex-M0 System Control register
– Set PDDS bit in Power Control register (PWR_CR)
– Clear WUF bit in Power Control/Status register (PWR_CSR)
Mode exit
WKUP pin rising edge, RTC alarm event’s rising edge, external Reset in
NRST pin, IWDG Reset.
Wakeup latency Reset phase
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