Digital-to-analog converter (DAC1) RM0091
208/742 Doc ID 018940 Rev 1
Figure 40. Timing diagram for conversion with trigger disabled TEN = 0
13.3.5 DAC output voltage
Digital inputs are converted to output voltages on a linear conversion between 0 and VDDA.
The analog output voltages on each DAC channel pin are determined by the following
equation:
13.3.6 DAC trigger selection
If the TENx control bit is set, conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8 possi-
ble events will trigger conversion as shown in Table 40.
Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on
the selected external interrupt line 9, the last data stored into the DAC_DHRx register are
transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1
cycles after the trigger occurs.
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
APB1_CLK
0x1AC
0x1AC
t
SETTLING
DHR
DOR
Output voltage
available on DAC_OUT pin
ai14711b
DACoutput V
DDA
DOR
4095
--------------
×=
Table 40. External triggers
Source Type TSEL[2:0]
Timer 6 TRGO event
Internal signal from on-chip
timers
000
Timer 3TRGO event 001
Reserved 010
Timer 15 TRGO event 011
Timer 2 TRGO event 100
Reserved 101
EXTI line9 External pin 110
SWTRIG Software control bit 111
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