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STMicroelectronics STM32F05 series User Manual

STMicroelectronics STM32F05 series
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HDMI-CEC controller (HDMI-CEC) RM0091
702/742 Doc ID 018940 Rev 1
Figure 292. Bit timings
28.4 Arbitration
All devices that wish to transmit - or retransmit - a message onto the CEC line have to
ensure that it has been inactive for a number of bit periods. This signal free time is defined
as the time starting from the final bit of the previous frame and depends on the initiating
device and the current status as shown in the table below.
Figure 293. Signal free time
Since only one initiator is allowed at any one time, an arbitration mechanism is provided to
avoid conflict when more than one initiator begins transmitting at the same time.
CEC line arbitration commences with the leading edge of the start bit and continues until the
end of the initiator address bits within the header block. During this period, the initiator shall
monitor the CEC line, if whilst driving the line to high impedance it reads it back to 0, it then
assumes it has lost arbitration, stops transmitting and becomes a follower.
Figure 294. Arbitration phase
START BIT
high impedance
low impedance
3.7ms +/-0.2ms
4.5ms +/-0.2ms
DATA BIT
high impedance
low impedance
1.5ms +/-0.2ms
2.4ms +/-0.35ms
INITIATOR LOGICAL 0
DATA BIT
high impedance
low impedance
0.6ms +/-0.2ms
2.4ms +/-0.35ms
INITIATOR LOGICAL 1
DATA BIT
high impedance
low impedance
0.35ms max
2.4ms +/-0.35ms
FOLLOWER LOGICAL 0
PREVIOUS MESSAGE NEW MESSAGE
Signal Free Time
START high impedance
BIT
EOM ACK
DESTINATION[3:0]INITIATOR[3:0]
Arbitration Phase

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STMicroelectronics STM32F05 series Specifications

General IconGeneral
BrandSTMicroelectronics
ModelSTM32F05 series
CategoryMicrocontrollers
LanguageEnglish

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