Reset and clock control (RCC) RM0091
86/742 Doc ID 018940 Rev 1
The timer clock frequencies are automatically fixed by hardware. There are two cases:
1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as
that of the APB domain.
2. otherwise, they are set to twice (×2) the frequency of the APB domain.
FCLK acts as Cortex-M0’s free-running clock. For more details refer to the ARM Cortex™-
M0 r0p0 technical reference manual(TRM).
7.2.1 HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock
sources:
● HSE external crystal/ceramic resonator
● HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
Figure 11. HSE/ LSE clock sources
Clock source Hardware configuration
External clock
Crystal/Ceramic
resonators
OSC_OUT
External
source
GPIO
OSC_IN
OSC_IN OSC_OUT
Load
capacitors
C
L2
C
L1
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