STMicroelectronics STM32F05 series User Manual

Reset and clock control (RCC) RM0091
102/742 Doc ID 018940 Rev 1
7.4.6 AHB peripheral clock enable register (RCC_AHBENR)
Address offset: 0x14
Reset value: 0x0000 0014
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
Bit 14 SPI2RST: SPI2 reset
Set and cleared by software.
0: No effect
1: Reset SPI2
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGRST: Window watchdog reset
Set and cleared by software.
0: No effect
1: Reset window watchdog
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 TIM14RST: TIM14 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM14
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 TIM6RST: TIM6 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM6
Bit 3:2 Reserved, must be kept at reset value.
Bit 1 TIM3RST: TIM3 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM3
Bit 0 TIM2RST: TIM2 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res Res Res Res Res Res Res TSCEN Res
IOPFE
N
Res
IOPD
EN
IOPC
EN
IOPB
EN
IOPA
EN
Res
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res Res Res Res Res Res Res Res Res
CRCE
N
Res
FLITF
EN
Res
SRAM
EN
Res
DMA
EN
rw rw rw rw

STMicroelectronics STM32F05 series Specifications

General

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English