RM0091 Advanced-control timers (TIM1)
Doc ID 018940 Rev 1 283/742
Note: The state of the external I/O pins connected to the complementary OCx and OCxN
channels depends on the OCx and OCxN channel state and the GPIO registers.
15.4.10 TIM1 counter (TIM1_CNT)
Address offset: 0x24
Reset value: 0x0000
15.4.11 TIM1 prescaler (TIM1_PSC)
Address offset: 0x28
Reset value: 0x0000
15.4.12 TIM1 auto-reload register (TIM1_ARR)
Address offset: 0x2C
Reset value: 0x0000
1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept
cleared.
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CNT[15:0]
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Bits 15:0 CNT[15:0]: Counter value
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PSC[15:0]
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Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency (CK_CNT) is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).
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ARR[15:0]
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Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 15.3.1: Time-base unit on page 225 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.
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