Inter-integrated circuit (I
2
C) interface RM0091
522/742 Doc ID 018940 Rev 1
23.7.2 Control register 2 (I2Cx_CR2)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res.
PEC
BYTE
AUTO
END
RE
LOAD
NBYTES[7:0]
rs rw rw rw
1514131211109876543210
NACK STOP START
HEAD
10R
ADD10
RD_W
RN
SADD[9:0]
rs rs rs rw rw rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bit 26
PECBYTE: Packet error checking byte
This bit is set by software, and cleared by hardware when the PEC is transferred, or
when a STOP condition or an Address Matched is received, also when PE=0 or
SWRST is set.
0: No PEC transfer.
1: PEC transmission/reception is requested
Note: Writing ‘0’ to this bit has no effect.
This bit has no effect when RELOAD is set.
This bit has no effect is slave mode when SBC=0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Please refer to Section 23.3: I2C implementation.
Bit 25 AUTOEND: Automatic end mode (master mode)
This bit is set and cleared by software.
0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.
1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are
transferred.
Note: This bit has no effect in slave mode or when the RELOAD bit is set.
Bit 24 RELOAD: NBYTES reload mode
This bit is set and cleared by software.
0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow).
1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded).
TCR flag is set when NBYTES data are transferred, stretching SCL low.
Bits 23:16 NBYTES[7:0]: Number of bytes
The number of bytes to be transmitted/received is programmed there. This field is don’t care
in slave mode with SBC=0.
Note: Changing these bits when the START bit is set is not allowed.
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