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RM0091 Analog-to-digital converter (ADC)

Doc ID 018940 Rev 1 201/742

12.12.8 ADC channel selection register (ADC_CHSELR)

Address offset: 0x28

Reset value: 0x0000 0000

12.12.9 ADC data register (ADC_DR)

Address offset: 0x40

Reset value: 0x0000 0000

Bit 11:0 LT[11:0]: Analog watchdog lower threshold

These bits are written by software to define the lower threshold for the analog watchdog.

Refer to Section 12.8: Analog window watchdog (AWDEN, AWDSGL, AWDCH, AWD_HTR/LTR,

AWD) on page 187

Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no

conversion is ongoing).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

CHSEL

rw rw

1514131211109876543210

CHSEL

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:0 CHSELx: Channel-x selection

These bits are written by software and define which channels are part of the sequence of channels to

be converted.

0: Input Channel-x is not selected for conversion

1: Input Channel-x is selected for conversion

Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no

conversion is ongoing).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

DATA[15:0]

rrrrrrrrrrrrrrrr

Bits 31:16 Reserved, must be kept at reset value.

STMicroelectronics STM32F05 series User Manual

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