EasyManuals Logo

STMicroelectronics STM32F05 series User Manual

STMicroelectronics STM32F05 series
742 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #501 background imageLoading...
Page #501 background image
RM0091 Inter-integrated circuit (I
2
C) interface
Doc ID 018940 Rev 1 501/742
23.4.11 SMBus specific features
This section is relevant only when SMBus feature is supported. Please refer to Table 23.3:
I2C implementation.
Introduction
The System Management Bus (SMBus) is a two-wire interface through which various
devices can communicate with each other and with the rest of the system. It is based on I2C
principles of operation. SMBus provides a control bus for system and power management
related tasks.
This peripheral is compatible with the SMBUS specification rev 2.0
(http://smbus.org/specs/).
The System Management Bus Specification refers to three types of devices.
A slave is a device that receives or responds to a command.
A master is a device that issues commands, generates the clocks and terminates the
transfer.
A host is a specialized master that provides the main interface to the system’s CPU. A
host must be a master-slave and must support the SMBus host notify protocol. Only
one host is allowed in a system.
This peripheral can be configured as master or slave device, and also as a host.
SMBUS is based on I2C specification rev 2.1.
Bus protocols
There are eleven possible command protocols for any given device. A device may use any
or all of the eleven protocols to communicate. The protocols are Quick Command, Send
Byte, Receive Byte, Write Byte, Write Word, Read Byte, Read Word, Process Call, Block
Read, Block Write and Block Write-Block Read Process Call. These protocols should be
implemented by the user software.
For more details of these protocols, refer to SMBus specification ver. 2.0
(http://smbus.org/specs/).
Address resolution protocol (ARP)
SMBus slave address conflicts can be resolved by dynamically assigning a new unique
address to each slave device. In order to provide a mechanism to isolate each device for the
purpose of address assignment each device must implement a unique device identifier
(UDID). This 128-bit number is implemented by software.
This peripheral supports the Address Resolution Protocol (ARP). The SMBus Device
Default Address (0b1100 001) is enabled by setting SMBDEN bit is I2Cx_CR1 register. The
ARP commands should be implemented by the user software.
Arbitration is also performed in slave mode for ARP support.
For more details of the SMBus Address Resolution Protocol, refer to SMBus specification
ver. 2.0 (http://smbus.org/specs/).

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the STMicroelectronics STM32F05 series and is the answer not in the manual?

STMicroelectronics STM32F05 series Specifications

General IconGeneral
BrandSTMicroelectronics
ModelSTM32F05 series
CategoryMicrocontrollers
LanguageEnglish

Related product manuals