STMicroelectronics STM32F05 series User Manual

Direct memory access controller (DMA) RM0091
148/742 Doc ID 018940 Rev 1
Figure 19. DMA request mapping
1. DMA request mapped on this DMA channel only if the corresponding remapping bit is cleared in the
SYSCFG_CFGR1 register. For more details, please refer to Section 9.1.1: SYSCFG configuration register
1 (SYSCFG_CFGR1) on page 135.
2. DMA request mapped on this DMA channel only if the corresponding remapping bit is set in the
SYSCFG_CFGR1 register. For more details, please refer to Section 9.1.1: SYSCFG configuration register
1 (SYSCFG_CFGR1) on page 135.
HW request 1
(MEM2MEM bit)
ADC
(1)
, TIM2_CH3,
TIM17_CH1,
TIM17_UP
(1)
Channel 1
Internal
DMA
request
Fixed hardware priority
ADC
(2)
, SPI1_RX,
USART1_TX ,
I2C1_TX, TIM1_CH1,
TIM2_UP, TIM3_CH3,
TIM17_CH1 ,
TIM17_UP
Peripheral request signals
High priority
Low priority
SPI1_TX,
USART1_RX
1
,
I2C1_RX, TIM1_CH2,
TIM2_CH2,
TIM3_CH4, TIM3_UP,
TIM6_UP, DAC,
TIM16_CH1 ,
TIM16_UP
SPI2_RX,
USART1_TX ,
I2C2_TX, USART2_TX,
TIM1_CH4,TIM1_TRIG,
TIM1_COM, TIM2_CH4,
TIM3_CH1,TIM3_TRIG,
TIM16_CH1 ,
TIM16_UP
SPI2_TX,
USART1_RX ,
I2C2_RX, USART2_RX,
TIM1_CH3, TIM1_UP,
TIM2_CH1, TIM15_CH1,
TIM15_UP,TIM15_TRIG,
TIM15_COM
DMA
MS19219V2
HW request 2 Channel 2
HW request 3 Channel 3
HW request 4
SW trigger
MEM2MEM bit)
Channel 4
HW request 5 Channel 5

SW trigger
MEM2MEM bit)

MEM2MEM bit) 
SW trigger
MEM2MEM bit)

(1)
(2)
(2)
()
1()
1
()
(2)
(2)
(2)
(2)
2
SW trigger
1
SW trigger 3
4
5

STMicroelectronics STM32F05 series Specifications

General

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English