RM0091 Cyclic redundancy check calculation unit (CRC)
Doc ID 018940 Rev 1 65/742
5.4.3 Control register (CRC_CR)
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res.
REV_O
UT
REV_IN[1:0] Res. Res. Res. RESET
rw rw rw rs
Bits 31:8 Reserved, must be kept cleared.
Bit 7 REV_OUT: Reverse output data
This bit controls the reversal of the bit order of the output data.
0: Bit order not affected
1: Bit-reversed output format
Bits 6:5 REV_IN[1:0]: Reverse input data
These bits control the reversal of the bit order of the input data
00: Bit order not affected
01: Bit reversal done by byte
10: Bit reversal done by half-word
11: Bit reversal done by word
Bits 4:3 Reserved, must be kept cleared.
Bits 4:3 These bits are generated only if the generic “full_poly” = 1 otherwise they are forced to 0
Bits 2:1 Reserved, must be kept cleared.
Bit 0 RESET: RESET bit
This bit is set by software to reset the CRC calculation unit and set the data register to the value stored
in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware
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