RM0091 Analog-to-digital converter (ADC)
Doc ID 018940 Rev 1 191/742
12.11 ADC interrupts
An interrupt can be generated by any of the following events:
● ADC power-up, when the ADC is ready (ADRDY flag)
● End of any conversion (EOC flag)
● End of a sequence of conversions (EOSEQ flag)
● When an analog watchdog detection occurs (AWD flag)
● When the end of sampling phase occurs (EOSMP flag)
● when a data overrun occurs (OVR flag)
Separate interrupt enable bits are available for flexibility.
Table 37. ADC interrupts
Interrupt event Event flag Enable control bit
ADC ready ADRDY ADRDYIE
End of conversion EOC EOCIE
End of sequence of conversions EOSEQ EOSEQIE
Analog watchdog status bit is set AWD AWDIE
End of sampling phase EOSMP EOSMPIE
Overrun OVR OVRIE
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