STMicroelectronics STM32F05 series User Manual

Reset and clock control (RCC) RM0091
104/742 Doc ID 018940 Rev 1
7.4.7 APB2 peripheral clock enable register (RCC_APB2ENR)
Address: 0x18
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB
domain is on going. In this case, wait states are inserted until the access to APB peripheral
is finished.
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
Bit 0 DMAEN: DMA clock enable
Set and cleared by software.
0: DMA clock disabled
1: DMA clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res Res Res Res Res Res Res Res Res
DBGM
CUEN
Res Res Res
TIM17
EN
TIM16
EN
TIM15
EN
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res
USART1
EN
Res
SPI1
EN
TIM1
EN
Res
ADC
EN
Res Res Res Res Res Res Res Res
SYSCFG
COMP
EN
rw rw rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DBGMCUEN MCU debug module clock enable
Set and reset by software.
0: MCU debug module clock disabled
1: MCU debug module enabled
Bits 21:19 Reserved, must be kept at reset value.
Bit 18 TIM17EN: TIM11 timer clock enable
Set and cleared by software.
0: TIM11 timer clock disabled
1: TIM11 timer clock enabled
Bit 17 TIM16EN: TIM10 timer clock enable
Set and cleared by software.
0: TIM10 timer clock disabled
1: TIM10 timer clock enabled
Bit 16 TIM15EN: TIM9 timer clock enable
Set and cleared by software.
0: TIM9 timer clock disabled
1: TIM9 timer clock enabled
Bit 15 Reserved, must be kept at reset value.

STMicroelectronics STM32F05 series Specifications

General

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English