RM0091 Inter-integrated circuit (I
2
C) interface
Doc ID 018940 Rev 1 487/742
23.4.9 I
2
C master mode
I2C master initialization
Before enabling the peripheral, the I2C master clock must be configured by setting the
SCLH and SCLL bits in the I2Cx_TIMINGR register.
A clock synchronization mechanism is implemented in order to support multi-master
environment and slave clock stretching.
In order to allow clock synchronization:
● The low level of the clock is counted using the SCLL counter, starting from the SCL low
level internal detection.
● The high level of the clock is counted using the SCLH counter, starting from the SCL
high level internal detection.
The I2C detects its own SCL low level after a
t
SYNC1
delay
depending on the SCL falling
edge, SCL input noise filters (analog + digital) and SCL synchronization to the I2Cx_CLK
clock. The I2C releases SCL to high level once the SCLL counter reaches the value
programmed in the SCLL[7:0] bits in the I2Cx_TIMINGR register.
The I2C detects its own SCL high level after a
t
SYNC2
delay depending on the SCL rising
edge, SCL input noise filters (analog + digital) and SCL synchronization to I2Cx_CLK clock.
The I2C ties SCL to low level once the SCLH counter is reached reaches the value
programmed in the SCLH[7:0] bits in the I2Cx_TIMINGR register.
Consequently the master clock period is:
t
SCL =
t
SYNC1
+ t
SYNC2 +
{ [(SCLH+1) + (SCLL+1)] x (PRESC+1) x t
I2CCLK
}
The duration of t
SYNC1
depends on these parameters:
– SCL falling slope
– When enabled, input delay induced by the analog filter.
– When enabled, input delay induced by the digital filter: DNF
x t
I2CCLK
– Delay due to SCL synchronization with I2CCLK clock (2 to 3 I2CCLK periods)
The duration of t
SYNC2
depends on these parameters:
– SCL rising slope
– When enabled, input delay induced by the analog filter.
– When enabled, input delay induced by the digital filter: DNF
x t
I2CCLK
– Delay due to SCL synchronization with I2CCLK clock (2 to 3 I2CCLK periods)
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