RM0091 Direct memory access controller (DMA)
Doc ID 018940 Rev 1 147/742
and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two
examples below:
● To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD”
with HSIZE = HalfWord
● To write the byte “0xAB”, the DMA sets the HWDATA bus to “0xABABABAB” with
HSIZE = Byte
Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the
HSIZE data into account, it will transform any AHB byte or halfword operation into a 32-bit
APB operation in the following manner:
● an AHB byte write operation of the data “0xB0” to 0x0 (or to 0x1, 0x2 or 0x3) will be
converted to an APB word write operation of the data “0xB0B0B0B0” to 0x0
● an AHB halfword write operation of the data “0xB1B0” to 0x0 (or to 0x2) will be
converted to an APB word write operation of the data “0xB1B0B1B0” to 0x0
For instance, if you want to write the APB backup registers (16-bit registers aligned to a 32-
bit address boundary), you must configure the memory source size (MSIZE) to “16-bit” and
the peripheral destination size (PSIZE) to “32-bit”.
10.3.5 Error management
A DMA transfer error can be generated by reading from or writing to a reserved address
space. When a DMA transfer error occurs during a DMA read or a write access, the faulty
channel is automatically disabled through a hardware clear of its EN bit in the corresponding
Channel configuration register (DMA_CCRx). The channel's transfer error interrupt flag
(TEIF) in the DMA_IFR register is set and an interrupt is generated if the transfer error
interrupt enable bit (TEIE) in the DMA_CCRx register is set.
10.3.6 Interrupts
An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for each
DMA channel. Separate interrupt enable bits are available for flexibility.
10.3.7 DMA request mapping
DMA controller
The hardware requests from the peripherals (TIMx, ADC, DAC, SPI, I2C, and USARTx) are
simply logically ORed before entering the DMA. This means that on one channel, only one
request must be enabled at a time. Refer to Figure 19: DMA request mapping.
The peripheral DMA requests can be independently activated/de-activated by programming
the DMA control bit in the registers of the corresponding peripheral.
Table 24. DMA interrupt requests
Interrupt event Event flag Enable control bit
Half-transfer HTIF HTIE
Transfer complete TCIF TCIE
Transfer error TEIF TEIE
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