STMicroelectronics STM32F05 series User Manual

RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S)
Doc ID 018940 Rev 1 669/742
can be generated if the ERRIE bit is set. The desynchronization flag (FRE) is cleared by
software when the status register is read.
26.6.8 I
2
S interrupts
Tabl e 93 provides the list of I
2
S interrupts.
26.6.9 DMA features
In I
2
S mode, the DMA works in exactly the same way as it does in SPI mode. There is no
difference except that the CRC feature is not available in I
2
S mode since there is no data
transfer protection system.
Table 93. I
2
S interrupt requests
Interrupt event Event flag Enable control bit
Transmit buffer empty flag TXE TXEIE
Receive buffer not empty flag RXNE RXNEIE
Overrun error OVR
ERRIEUnderrun error UDR
Frame error flag FRE

STMicroelectronics STM32F05 series Specifications

General

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English