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Reset and clock control (RCC) RM0091

114/742 Doc ID 018940 Rev 1

7.4.13 Clock configuration register 3 (RCC_CFGR3)

Address: 0x30

Reset value: 0x0000 0000

Access: no wait states, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res Res Res Res Res Res Res

ADC

Res

CEC

Res

I2C1

Res Res USART1SW[1:0]

rw rw rw rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 ADCSW: ADC clock source selection

This bit is set and cleared by software to select ADC clock source.

0: HSI14 clock selected as ADC kernel clock (default)

1: PLCK divided by 2 or 4, selected as ADC clock

Note: When HSI14 is selected as ADC clock source, the HSI14 oscillator must not be

disabled (HSI14DIS=0 in the Clock control register 2 (RCC_CR2)).

Bit 7 Reserved, must be kept at reset value.

Bit 6 CECSW: HDMI CEC clock source selection

This bit is set and cleared by software to select the CEC clock source.

0: HSI clock, divided by 244, selected as CEC clock (default)

1: LSE clock selected as CEC clock

Bit 5 Reserved, must be kept at reset value.

Bit 4 I2C1SW: I2C1 clock source selection

This bit is set and cleared by software to select the I2C1 clock source.

0: HSI clock selected as I2C1 clock source (default)

1: System clock (SYSCLK) selected as I2C1 clock

Bits 3:2 Reserved, must be kept at reset value.

Bits 1:0 USART1SW[1:0]: USART1 clock source selection

This bit is set and cleared by software to select the USART1 clock source.

00: PCLK selected as USART1 clock source (default)

01: System clock (SYSCLK) selected as USART1 clock

10: LSE clock selected as USART1 clock

11: HSI clock selected as USART1 clock

STMicroelectronics STM32F05 series User Manual

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