STMicroelectronics STM32F05 series - Figure 57. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0 X6; Figure 58. Counter Timing Diagram, Internal Clock Divided by 2; Figure 59. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0 X36

RM0091 Advanced-control timers (TIM1)
Doc ID 018940 Rev 1 233/742
Figure 57. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
1. Here, center-aligned mode 1 is used (for more details refer to Section 15.4: TIM1 registers on page 265).
Figure 58. Counter timing diagram, internal clock divided by 2
Figure 59. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
CK_PSC
02
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter underflow
Update event (UEV)
03 04 05 06 05 04 0303 02 01 00 0104
Counter overflow
CK_PSC
0002 0000 0001 0002 0003
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0003
0001
Counter underflow
Update event (UEV)
CK_PSC
0036 0035
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0034
0035
Counter overflow
Update event (UEV)