Analog-to-digital converter (ADC) RM0091
176/742 Doc ID 018940 Rev 1
12.4.8 Continuous conversion mode (CONT=1)
In continuous conversion mode, when a software or hardware trigger event occurs, the ADC
performs a sequence of conversions, converting all the channels once and then
automatically re-starts and continuously performs the same sequence of conversions. This
mode is selected when CONT=1 in the ADC_CFGR1 register. Conversion is started by
either:
● Setting the ADSTART bit in the ADC_CR register
● Hardware trigger event
Inside the sequence, after each conversion is complete:
● The converted data are stored in the 16-bit ADC_DR register
● The EOC (end of conversion) flag is set
● An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
● The EOSEQ (end of sequence) flag is set
● An interrupt is generated if the EOSEQIE bit is set
Then, a new sequence restarts immediately and the ADC continuously repeats the
conversion sequence.
Note: 1 To convert a single channel, program a sequence with a length of 1.
2 It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN=1 and CONT=1.
12.4.9 Starting conversions (ADSTART)
Software starts ADC conversions by setting ADSTART=1.
When ADSTART is set, the conversion:
● Starts immediately if EXTEN = 0x0 (software trigger)
● At the next active edge of the selected hardware trigger if EXTEN ≠ 0x0
The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing. It
is possible to re-configure the ADC while ADSTART=0, indicating that the ADC is idle.
The ADSTART bit is cleared by hardware:
● In single mode with software trigger (CONT=0, EXTSEL=0x0)
– At any end of conversion sequence (EOSEQ=1)
● In all cases (CONT=x, EXTSEL=x)
– After execution of the ADSTP procedure invoked by software (see
Section 12.4.11: Stopping an ongoing conversion (ADSTP) on page 177.
Note: 1 In continuous mode (CONT=1), the ADSTART bit is not cleared by hardware when the
EOSEQ flag is set because the sequence is automatically relaunched.
2 When hardware trigger is selected in single mode (CONT=0 and EXTSEL
≠ 0x00),
ADSTART is not cleared by hardware when the EOSEQ flag is set. This avoids the need for
software having to set the ADSTART bit again and ensures the next trigger event is not
missed.
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