RM0091 Debug support (DBG)
Doc ID 018940 Rev 1 729/742
29.9.4 Debug MCU APB low freeze register (DBGMCU_APB1_FZ)
The DBGMCU_APB1_FZ register is used to configure the MCU under DEBUG. It concerns
some APB peripherals:
● Timer clock counter freeze
● I2C SMBUS timeout freeze
● Window watchdog and independent watchdog counter freeze support
This DBGMCU_APB1_FZ is mapped at address 0x4001 5808.
The register is asynchronously reset by the POR (and not the system reset). It can be
written by the debugger under system reset.
Address offset: 0x08
Only 32-bit access are supported.
Power on reset (POR): 0x0000 0000 (not reset by system reset)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG_I2C1_SMBUS_TIMEOUT
Res. Res. Res. Res. Res.
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res.
DBG_IWDG_STOP
DBG_WWDG_STOP
DBG_RTC_STOP
Res.
DBG_TIM14_STOP
Res. Res. Res.
DBG_TIM6_STOP
Res. Res.
DBG_TIM3_STOP
DBG_TIM2_STOP
rw rw rw rw rw rw rw
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 DBG_I2C1_SMBUS_TIMEOUT: SMBUS timeout mode stopped when core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 DBG_IWDG_STOP: Debug independent watchdog stopped when core is halted
0: The independent watchdog counter clock continues even if the core is halted
1: The independent watchdog counter clock is stopped when the core is halted
Bit 11 DBG_WWDG_STOP: Debug window watchdog stopped when core is halted
0: The window watchdog counter clock continues even if the core is halted
1: The window watchdog counter clock is stopped when the core is halted
Bit 10 DBG_RTC_STOP: Debug RTC stopped when core is halted
0: The clock of the RTC counter is fed even if the core is halted
1: The clock of the RTC counter is stopped when the core is halted
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