RM0091 General-purpose timers (TIM2 and TIM3)
Doc ID 018940 Rev 1 325/742
In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts
from 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both
timers. Timer 2 stops when Timer 1 is disabled by writing ‘0 to the CEN bit in the TIM1_CR1
register:
● Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIM1_CR2 register).
● Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).
● Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR
register).
● Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).
● Reset Timer 1 by writing ‘1 in UG bit (TIM1_EGR register).
● Reset Timer 2 by writing ‘1 in UG bit (TIM2_EGR register).
● Initialize Timer 2 to 0xE7 by writing ‘0xE7’ in the timer 2 counter (TIM2_CNTL).
● Enable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).
● Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).
● Stop Timer 1 by writing ‘0 in the CEN bit (TIM1_CR1 register).
Figure 133. Gating timer 2 with Enable of timer 1
TIMER 2-TIF
Write TIF=0
75 00 01
CK_INT
TIMER1-CEN=CNT_EN
TIMER1-CNT
TIMER2-CNT
02
TIMER1-CNT_INIT
AB 00 E7 E8 E9
TIMER2-CNT_INIT
TIMER2
write CNT
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