Embedded Flash memory RM0091
54/742 Doc ID 018940 Rev 1
3.5.3 Flash option key register (FLASH_OPTKEYR)
Address offset: 0x08
Reset value: xxxx xxxx
All the register bits are all write-only and will return a 0 when read.
3.5.4 Flash status register (FLASH_SR)
Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEYR[31:16]
wwwwwww wwwwwwwww
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEYR[15:0]
wwwwwww wwwwwwwww
Bits 31:0 OPTKEYR: Option byte key
These bits represent the keys to unlock the OPTWRE.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EOP
WRPRT
ERR
Res.
PG
ERR
Res. BSY
rw rw rw r
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 EOP: End of operation
Set by hardware when a Flash operation (programming / erase) is completed.
Reset by writing a 1
Note: EOP is asserted at the end of each successful program or erase operation
Bit 4 WRPRTERR: Write protection error
Set by hardware when programming a write-protected address of the Flash
memory.
Reset by writing 1.
Bit 3 Reserved, must be kept at reset value.
Bit 2 PGERR: Programming error
Set by hardware when an address to be programmed contains a value different
from '0xFFFF' before programming.
Reset by writing 1.
Note: The STRT bit in the FLASH_CR register should be reset before starting a
programming operation.
Bit 1 Reserved, must be kept at reset value
Bit 0 BSY: Busy
This indicates that a Flash operation is in progress. This is set on the beginning
of a Flash operation and reset when the operation finishes or when an error
occurs.
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