Debug support (DBG) RM0091
726/742 Doc ID 018940 Rev 1
These registers are not reset by a system reset. They are only reset by a power-on reset.
Refer to the Cortex-M0 TRM for further details.
To Halt on reset, it is necessary to:
● enable the bit0 (VC_CORRESET) of the Debug and Exception Monitor Control
Register
● enable the bit0 (C_DEBUGEN) of the Debug Halting Control and Status Register.
29.7 BPU (Break Point Unit)
The Cortex-M0 BPU implementation provides four breakpoint registers. The BPU is a
subset of the Flash Patch and Breakpoint (FPB) block available in ARMv7-M (Cortex-M3 &
Cortex-M4).
29.7.1 BPU functionality
The processor breakpoints implement PC based breakpoint functionality.
Refer the ARMv6-M ARM and the ARM CoreSight Components Technical Reference
Manual for more information about the BPU CoreSight identification registers, and their
addresses and access types.
29.8 DWT (Data Watchpoint)
The Cortex-M0 DWT implementation provides two watchpoint register sets.
29.8.1 DWT functionality
The processor watchpoints implement both data address and PC based watchpoint
functionality, a PC sampling register, and support comparator address masking, as
described in the ARMv6-M ARM.
29.8.2 DWT Program Counter Sample Register
A processor that implements the data watchpoint unit also implements the ARMv6-M
optional DWT Program Counter Sample Register (DWT_PCSR). This register permits a
debugger to periodically sample the PC without halting the processor. This provides coarse
grained profiling. See the ARMv6-M ARM for more information.
The Cortex-M0 DWT_PCSR records both instructions that pass their condition codes and
those that fail.
29.9 MCU debug component (DBGMCU)
The MCU debug component helps the debugger provide support for:
● Low-power modes
● Clock control for timers, watchdog and I2C during a breakpoint
● Control of the trace pins assignment
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