General-purpose timers (TIM15/16/17) RM0091
384/742 Doc ID 018940 Rev 1
Figure 162. Update rate examples depending on mode and TIMx_RCR register
settings
18.4.4 Clock sources
The counter clock can be provided by the following clock sources:
● Internal clock (CK_INT)
● External clock mode1: external input pin
● Internal trigger inputs (ITRx) (only for TIM15): using one timer as the prescaler for
another timer, for example, you can configure TIM1 to act as a prescaler for TIM15.
Refer to Using one timer as prescaler for another for more details.
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 17.3.4 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
Edge-aligned mode
UEV
UEV
UEV
UEV
UEV
Update Event
: Preload registers transferred to active registers and update interrupt generated
Counter
TIMx_RCR = 0
TIMx_RCR = 1
TIMx_RCR = 2
TIMx_RCR = 3
UEV
TIMx_RCR
= 3
and
re-synchronization
(by SW)
TIMx_CNT
Upcounting
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