STMicroelectronics STM32F05 series - Spix_I 2 S Configuration Register (Spix_I2 Scfgr)

Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091
678/742 Doc ID 018940 Rev 1
26.7.8 SPIx_I
2
S configuration register (SPIx_I2SCFGR)
Address offset: 0x1C
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. I2SMOD I2SE I2SCFG
PCMSY
NC
Res. I2SSTD CKPOL DATLEN CHLEN
rw rw rw rw rw rw rw rw rw rw rw
Bits 15:12 Reserved: Forced to 0 by hardware
Bit 11 I2SMOD: I2S mode selection
0: SPI mode is selected
1: I2S mode is selected
Note: This bit should be configured when the SPI or I
2
S is disabled
Bit 10 I2SE: I2S enable
0: I
2
S peripheral is disabled
1: I
2
S peripheral is enabled
Note: Not used in SPI mode
Bits 9:8 I2SCFG: I2S configuration mode
00: Slave - transmit
01: Slave - receive
10: Master - transmit
11: Master - receive
Note: This bit should be configured when the I
2
S is disabled.
Not used for the SPI mode
Bit 7 PCMSYNC: PCM frame synchronization
0: Short frame synchronization
1: Long frame synchronization
Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used)
Not used for the SPI mode
Bit 6 Reserved: forced at 0 by hardware
Bits 5:4 I2SSTD: I
2
S standard selection
00: I
2
S Philips standard.
01: MSB justified standard (left justified)
10: LSB justified standard (right justified)
11: PCM standard
For more details on I
2
S standards, refer to Section 26.6.2 on page 654
Note: For correct operation, these bits should be configured when the I
2
S is disabled.
Not used in SPI mode
Bit 3 CKPOL: Steady state clock polarity
0: I
2
S clock steady state is low level
1: I
2
S clock steady state is high level
Note: For correct operation, this bit should be configured when the I
2
S is disabled.
Not used in SPI mode