Analog-to-digital converter (ADC) RM0091
188/742 Doc ID 018940 Rev 1
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can
be enabled by setting the AWDIE bit in the ADC_IER register.
The AWD flag is cleared by software by writing 1 to it.
When converting a data with a resolution of less than 12-bit (according to bits DRES[1:0]),
the LSB of the programmed thresholds must be kept cleared because the internal
comparison is always performed on the full 12-bit raw converted data (left aligned).
Tabl e 35 describes how the comparison is performed for all the possible resolutions.
Tabl e 36 shows how to configure the AWDSGL and AWDEN bits in the ADC_CFGR1
register to enable the analog watchdog on one or more channels.
Figure 36. Analog watchdog guarded area
Table 35. Analog watchdog comparison
Resolutio
n
bits
RES[1:0]
Analog Watchdog comparison between:
Comments
Raw converted
data, left
aligned
(1)
Thresholds
00: 12-bit DATA[11:0] LT[11:0] and HT[11:0] -
01: 10-bit DATA[11:2],00 LT[11:0] and HT[11:0] The user must configure LT1[1:0] and HT1[1:0] to “00”
10: 8-bit DATA[11:4],0000 LT[11:0] and HT[11:0]
The user must configure LT1[3:0] and HT1[3:0] to
“0000”
11: 6-bit DATA[11:6],000000 LT[11:0] and HT[11:0]
The user must configure LT1[5:0] and HT1[5:0] to
“000000”
1. The watchdog comparison is performed on the raw converted data before any alignment calculation.
Table 36. Analog watchdog channel selection
Channels guarded by the analog watchdog AWDSGL bit AWDEN bit
None x 0
All channels 0 1
Single
(1)
channel
1. Selected by the AWDCH[4:0] bits
11
Analog voltage
Higher threshold
Lower threshold
Guarde d area
HTR
LTR
ai16048
To Next Page
Loading...
Need help?
General
