STMicroelectronics STM32F05 series User Manual

RM0091 Direct memory access controller (DMA)
Doc ID 018940 Rev 1 149/742
Tabl e 25 lists the DMA requests for each channel.
Table 25. Summary of DMA requests for each channel
Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
ADC ADC
(1)
ADC
(2)
SPI SPI1_RX SP1_TX SPI2_RX SPI2_TX
USART USART1_TX
(1)
USART1_RX
(1)
USART1_TX
(2)
USART2_TX
USART1_RX
(2)
USART2_RX
I2C I2C1_TX I2C1_RX I2C2_TX I2C2_RX
TIM1 TIM1_CH1 TIM1_CH2
TIM1_CH4
TIM1_TRIG
TIM1_COM
TIM1_CH3
TIM1_UP
TIM2 TIM2_CH3 TIM2_UP TIM2_CH2 TIM2_CH4 TIM2_CH1
TIM3 TIM3_CH3
TIM3_CH4
TIM3_UP
TIM3_CH1
TIM3_TRIG
TIM6 / DAC
TIM6_UP
DAC
TIM15
TIM15_CH1
TIM15_UP
TIM15_TRIG
TIM15_COM
TIM16
TIM16_CH1
(1)
TIM16_UP
(1)
TIM16_CH1
(2)
TIM16_UP
(2)
TIM17
TIM17_CH1
(1)
TIM17_UP
(1)
TIM17_CH1
(2)
TIM17_UP
(2)
1. DMA request mapped on this DMA channel only if the corresponding remapping bit is cleared in the SYSCFG_CFGR1
register. For more details, please refer to Section 9.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1) on page 135.
2. DMA request mapped on this DMA channel only if the corresponding remapping bit is set in the SYSCFG_CFGR1 register.
For more details, please refer to Section 9.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1) on page 135.

STMicroelectronics STM32F05 series Specifications

General

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English