STMicroelectronics STM32F05 series User Manual

RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S)
Doc ID 018940 Rev 1 639/742
Figure 257. Master and three independent slaves
1. As MISO pins of the slaves are connected together, all slaves must have the GPIO configuration of their
MISO pin set as alternate function open-drain (see Section 8.3.7: I/O alternate function input/output on
page 123.
26.3.4 Slave select (NSS) pin management
In slave mode, the NSS works as a standard “chip select” input and lets the slave
communicate with the master. In master mode, NSS can be used either as output or input.
As an input it can prevent multimaster bus collision, and as an output it can drive a slave
select signal of a single slave.
shift register
SPI clock
generator
SCK
MOSI
MISO
SCK
MOSI
MISO
Master
Slave 1
shift register
shift register
MS19830V1
NSS
SCK
MOSI
MISO
Slave 2
NSS
SCK
MOSI
MISO
Slave 3
shift register
I/O 1
I/O 2
I/O 3
NSS
NSS
(1)
Vcc

STMicroelectronics STM32F05 series Specifications

General

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English