STMicroelectronics STM32F05 series User Manual

RM0091 Reset and clock control (RCC)
Doc ID 018940 Rev 1 105/742
7.4.8 APB1 peripheral clock enable register (RCC_APB1ENR)
Address: 0x1C
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
Bit 14 USART1EN: USART1clock enable
Set and cleared by software.
0: USART1clock disabled
1: USART1clock enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 TIM1EN: TIM1 timer clock enable
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1P timer clock enabled
Bit 10 Reserved, must be kept at reset value.
Bit 9 ADCEN: ADC interface clock enable
Set and cleared by software.
0: ADC interface disabled
1: ADC interface clock enabled
Bits 8:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGCOMPEN: SYSCFG clock enable
Set and cleared by software.
0: SYSCFG clock disabled
1: SYSCFG clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res
CEC
EN
DAC
EN
PWR
EN
Res Res Res Res Res
I2C2
EN
I2C1
EN
Res Res Res
USART
2EN
Res
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res
SPI2
EN
Res Res
WWD
GEN
Res Res
TIM14
EN
Res Res Res
TIM6
EN
Res Res
TIM3
EN
TIM2
EN
rw rw rw rw rw rw

STMicroelectronics STM32F05 series Specifications

General

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English