STMicroelectronics STM32F05 series User Manual

RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S)
Doc ID 018940 Rev 1 649/742
consecutive data frame transfers when NSS stays at high level for the duration of one clock
period at least. This mode allows the slave to latch data. NSSP pulse mode is designed for
applications with a single master-slave pair.
Figure 262 illustrates NSS pin management when NSSP pulse mode is enabled.
Figure 262. NSSP pulse generation in Motorola SPI master mode
Note: Similar behavior is encountered when CPOL = 0. In this case the sampling edge is the rising
edge of SCK, and NSS assertion and deassertion refer to this sampling edge.
26.4.2 TI mode
TI protocol in master mode
The SPI interface is compatible with the TI protocol. The FRF bit of the SPIx_CR2 register
can be used to configure the SPI to be compliant with this protocol.
The clock polarity and phase are forced to conform to the TI protocol requirements whatever
the values set in the SPIx_CR1 register. NSS management is also specific to the TI protocol
which makes the configuration of NSS management through the SPIx_CR1 and SPIx_CR2
registers (SSM, SSI, SSOE) impossible in this case.
In slave mode, the SPI baud rate prescaler is used to control the moment when the MISO
pin state changes to HiZ. Any baud rate can be used, making it possible to determine this
moment with optimal flexibility. However, the baud rate is generally set to the external master
clock baud rate. The delay for the MISO signal to become HiZ (t
release
) depends on internal
resynchronization and on the baud rate value set in through the BR[2:0] bits in the
SPIx_CR1 register. It is given by the formula:
This feature is not available for Motorola SPI communications (FRF bit set to 0).
Figure 263: TI mode transfer shows the SPI communication waveforms when TI mode is
selected.
MS19838V1
MOSI
output
NSS
output
SCK
output
sampling
MISO
input
DONTCARE
MSB
MSB
4-bits to 16-bits
DONTCARE
LSB
LSB
MSB
MSB
LSB
LSB
4-bits to 16-bits
DONTCARE
Master conti nuous trans fer (CPOL = 1 ; CPHA =0 ; NSSP =1)
sampling sampling sampling sampling sampling
t
SCK
t
SCK
t
SCK
t
SCK
t
SCK
t
baud_rate
2
---------------------- 4t
pclk
×+ t
release
t
baud_rate
2
---------------------- 6t
pclk
×+<<

STMicroelectronics STM32F05 series Specifications

General

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English