RM0091 Direct memory access controller (DMA)
Doc ID 018940 Rev 1 143/742
The block diagram is shown in the following figure.
Figure 18. DMA block diagram
10.3 DMA functional description
The DMA controller performs direct memory transfer by sharing the system bus with the
Cortex-M0 core. The DMA request may stop the CPU access to the system bus for some
bus cycles, when the CPU and DMA are targeting the same destination (memory or
peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half
of the system bus bandwidth (both to memory and peripheral) for the CPU.
10.3.1 DMA transactions
After an event, the peripheral sends a request signal to the DMA Controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA
Controller. The peripheral releases its request as soon as it gets the Acknowledge from the
DMA Controller. Once the request is deasserted by the peripheral, the DMA Controller
release the Acknowledge. If there are more requests, the peripheral can initiate the next
transaction.
In summary, each DMA transfer consists of three operations:
● The loading of data from the peripheral data register or a location in memory
addressed through an internal current peripheral/memory address register. The start
FLITF
Ch.1
Ch.2
Ch.7
Arbiter
Cortex-M0
SRAM
AHB Slave
DMA
APB
Flash
Bridge
MS19218V1
Bus matrix
DMA
Reset & clock
control (RCC)
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOH
CRC
System
ADC3
USART1
TIM8
SPI1
TIM1
ADC2
ADC1
GPIOB
GPIOA
EXTI
AFIO
DAC SPI3/I2S
TIM2
PWR
BKP
bxCAN
USB
I2C2
I2C1
UART5
UART4
USART3
USART2
SPI2/I2S
IWDG
WWDG
RTC
TIM7
TIM6
TIM5
TIM4
TIM3
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