STMicroelectronics STM32F05 series User Manual

Universal synchronous asynchronous receiver transmitter (USART) RM0091
594/742 Doc ID 018940 Rev 1
Figure 238. Break detection in LIN mode vs. Framing error detection
25.5.11 USART synchronous mode
The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to
1. In synchronous mode, the following bits must be kept cleared:
● LINEN bit in the USART_CR2 register,
● SCEN, HDSEL and IREN bits in the USART_CR3 register.
In this mode, the USART can be used to control bidirectional synchronous serial
communications in master mode. The SCLK pin is the output of the USART transmitter
clock. No clock pulses are sent to the SCLK pin during start bit and stop bit. Depending on
the state of the LBCL bit in the USART_CR2 register, clock pulses are, or are not, generated
during the last valid data bit (address mark). The CPOL bit in the USART_CR2 register is
used to select the clock polarity, and the CPHA bit in the USART_CR2 register is used to
select the phase of the external clock (see Figure 239, Figure 240 & Figure 241).
During the Idle state, preamble and send break, the external SCLK clock is not activated.
In synchronous mode the USART transmitter works exactly like in asynchronous mode. But
as SCLK is synchronized with TX (according to CPOL and CPHA), the data on TX is
synchronous.
In this mode the USART receiver works in a different manner compared to the
asynchronous mode. If RE=1, the data is sampled on SCLK (rising or falling edge,
depending on CPOL and CPHA), without any oversampling. A setup and a hold time must
be respected (which depends on the baud rate: 1/16 bit time).
Note: The SCLK pin works in conjunction with the TX pin. Thus, the clock is provided only if the
transmitter is enabled (TE=1) and data is being transmitted (the data register USART_DR
written). This means that it is not possible to receive synchronous data without transmitting
data.
The LBCL, CPOL and CPHA bits have to be selected when the USART is disabled (UE=0)
to ensure that the clock pulses function correctly.
Case 1: break occurring after an Idle
IDLE data2 (0x55)data 1 data 3 (header)
In these examples, we suppose that LBDL=1 (11-bit break length), M=0 (8-bit data)
RX line
RXNE / FE
LBDF
1 data time 1 data time
Case 1: break occurring while data is being received
data 2 data2 (0x55)data 1 data 3 (header)
RX line
RXNE / FE
LBDF
1 data time 1 data time
BREAK
BREAK

STMicroelectronics STM32F05 series Specifications

General

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English