System configuration controller (SYSCFG) RM0091
140/742 Doc ID 018940 Rev 1
9.1.7 SYSCFG register maps
The following table gives the SYSCFG register map and the reset values.
Bits 31:9 Reserved, must be kept at reset value
Bit 8 SRAM_PEF: SRAM parity flag
This bit is set by hardware when an SRAM parity error is detected. It is cleared
by software by writing ‘1’.
0: No SRAM parity error detected
1: SRAM parity error detected
Bits 7:3 Reserved, must be kept at reset value
Bit 2 PVD_LOCK: PVD lock enable bit
This bit is set by software and cleared by a system reset. It can be used to
enable and lock the PVD connection to TIM1/15/16/17 Break input, as well as
the PVDE and PLS[2:0] in the PWR_CR register.
0: PVD interrupt disconnected from TIM1/15/16/17 Break input. PVDE and
PLS[2:0] bits can be programmed by the application.
1: PVD interrupt connected to TIM1/15/16/17 Break input, PVDE and PLS[2:0]
bits are read only.
Bit 1 SRAM_PARITY_LOCK: SRAM parity lock bit
This bit is set by software and cleared by a system reset. It can be used to
enable and lock the SRAM parity error signal connection to TIM1/15/16/17 Break
input.
0: SRAM parity error disconnected from TIM1/15/16/17 Break input
1: SRAM parity error connected to TIM1/15/16/17 Break input
Bit 0 LOCKUP_LOCK: Cortex-M0 LOCKUP bit enable bit
This bit is set by software and cleared by a system reset. It can be use to enable
and lock the connection of Cortex-M0 LOCKUP (Hardfault) output to
TIM1/15/16/17 Break input.
0: Cortex-M0 LOCKUP output disconnected from TIM1/15/16/17 Break input
1: Cortex-M0 LOCKUP output connected to TIM1/15/16/17 Break input
Table 22. SYSCFG register map and reset values
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
SYSCFG_CFGR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
I2C_PB9_FM+
I2C_PB8_FM+
I2C_PB7_FM+
I2C_PB6_FM+
Res.
Res.
Res.
TIM17_DMA_RMP
TIM16_DMA_RMP
USART1_RX_DMA_RMP
USART1_TX_DMA_RMP
ADC_DMA_RMP
Res.
Res.
Res.
Res.
Res.
Res.
MEM_MODE
Reset value rwrwrwrw rwrwrwrwrw X X
0x08
SYSCFG_EXTICR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]
Reset value 0000000000000000
0x0C
SYSCFG_EXTICR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]
Reset value 0000000000000000
0x10
SYSCFG_EXTICR3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]
Reset value 0000000000000000
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