Inter-integrated circuit (I
2
C) interface RM0091
476/742 Doc ID 018940 Rev 1
Figure 199. I2C initialization flowchart
23.4.6 Software reset
A software reset can be performed by setting the SWRST bit in the I2Cx_CR1 register. In
that case I2C lines SCL and SDA are released. Internal states machines are reset and
communication control bits, as well as status bits come back to their reset value. The
configuration registers are not impacted.
Here is the list of impacted register bits:
1. I2Cx_CR2 register: START, STOP, NACK
2. I2Cx_ISR register: BUSY, TXE, TXIS, RXNE, ADDR, NACKF, TCR, TC, STOPF, BERR,
ARLO, OVR
and in addition when the SMBus feature is supported:
1. I2Cx_CR2 register: PECBYTE
2. I2Cx_ISR register: PECERR, TIMEOUT, ALERT
MS19847V1
Clear PE bit in I2Cx_CR1
Initial settings
Configure ANFOFF and DNF[3:0] in I2Cx_CR1
Configure PRESC[3:0],
SDADEL[3:0], SCLDEL[3:0], SCLH[7:0],
SCLL[7:0] in I2Cx_TIMINGR
Configure NOSTRETCH in I2Cx_CR1
Set PE bit in I2Cx_CR1
End
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