RM0091 Debug support (DBG)
Doc ID 018940 Rev 1 731/742
29.9.5 Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
The DBGMCU_APB2_FZ register is used to configure the MCU under DEBUG. It concerns
some APB peripherals:
● Timer clock counter freeze
This register is mapped at address 0x4001580C.
It is asynchronously reset by the POR (and not the system reset). It can be written by the
debugger under system reset.
Address offset: 0x0C
Only 32-bit access is supported.
POR: 0x0000 0000 (not reset by system reset)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG_TIM17_STOP
DBG_TIM16_STOP
DBG_TIM15_STOP
rw rw rw
1514131211109876543 2 1 0
Res. Res. Res. Res.
DBG_TIM1_STOP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 DBG_TIM17_STOP: TIM17 counter stopped when core is halted
0: The counter clock of TIM17 is fed even if the core is halted
1: The counter clock of TIM17 is stopped when the core is halted
Bit 17 DBG_TIM16_STOP: TIM16 counter stopped when core is halted
0: The counter clock of TIM16 is fed even if the core is halted
1: The counter clock of TIM16 is stopped when the core is halted
Bit 16 DBG_TIM15_STOP: TIM15 counter stopped when core is halted
0: The counter clock of TIM15 is fed even if the core is halted
1: The counter clock of TIM15 is stopped when the core is halted
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 DBG_TIM1_STOP: TIM1 counter stopped when core is halted
0: The counter clock of TIM 1 is fed even if the core is halted
1: The counter clock of TIM 1 is stopped when the core is halted
Bits 0:10 Reserved, must be kept at reset value.
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