STMicroelectronics STM32F05 series User Manual

Interrupts and events RM0091
160/742 Doc ID 018940 Rev 1
Figure 20. EXTI external interrupt/event block diagram
11.2.3 Wakeup event management
The STM32F05xxx is able to handle external or internal events in order to wake up the core
(WFE). The wakeup event can be generated either by:
● enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex-M0 System Control register. When the MCU
resumes from WFE, the EXTI peripheral interrupt pending bit and the peripheral NVIC
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared.
● or by configuring an external or internal EXTI line in event mode. When the CPU
resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or
the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is
not set.
11.2.4 Asynchronous Internal Interrupts
Some communication peripherals (UART, I2C, CEC) are able to generate events when the
system is in run mode and also when the system is in stop mode allowing to wake up the
system from stop mode.
To accomplish this, the peripheral is asked to generate both a synchronized (to the system
clock, e.g. APB clock) and an asynchronous version of the event.
Peripheral interface
Edge detect
circuit
AMBA APB bus
PCLK
23
23 23
2323
23
23
To NVIC interrupt
controller
Software
interrupt
event
Register
Rising
trigger
selection
regsiter
23
Event
mask
register
Pulse
generator
23
23
23
23
Input
line
Pending
request
register
23
MS19952V1
Interrupt
mask
register
Falling
trigger
selection
regsiter

STMicroelectronics STM32F05 series Specifications

General

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English