Analog-to-digital converter (ADC) RM0091
200/742 Doc ID 018940 Rev 1
12.12.6 ADC sampling time register (ADC_SMPR)
Address offset: 0x14
Reset value: 0x0000 0000
12.12.7 ADC watchdog threshold register (ADC_TR)
Address offset: 0x20
Reset value: 0x0000 0FFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMP[2:0]
rw
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 SMP[2:0]: Sampling time selection
These bits are written by software to select the sampling time that applies to all channels.
000: 1.5 ADC clock cycles
001: 7.5 ADC clock cycles
010: 13.5 ADC clock cycles
011: 28.5 ADC clock cycles
100: 41.5 ADC clock cycles
101: 55.5 ADC clock cycles
110: 71.5 ADC clock cycles
111: 239.5 ADC clock cycles
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. HT[11:0]
1514131211109876543210
Res. Res. Res. Res. LT[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bit 27:16 HT[11:0]: Analog watchdog higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to Section 12.8: Analog window watchdog (AWDEN, AWDSGL, AWDCH, AWD_HTR/LTR,
AWD) on page 187
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 15:12 Reserved, must be kept at reset value.
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