RM0091 General-purpose timers (TIM15/16/17)
Doc ID 018940 Rev 1 403/742
18.5.2 TIM15 control register 2 (TIM15_CR2)
Address offset: 0x04
Reset value: 0x0000
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock and gated mode can work only if the CEN bit has been previously set by
software. However trigger mode can set the CEN bit automatically by hardware.
1514131211109876543210
Res. Res. Res. Res. Res. OIS2 OIS1N OIS1 Res. MMS[2:0] CCDS CCUS Res. CCPC
rw rw rw rw rw rw rw rw rw
Bit 15:11 Reserved, always read as 0.
Bit 10 OIS2: Output idle state 2 (OC2 output)
0: OC2=0 when MOE=0
1: OC2=1 when MOE=0
Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in the TIMx_BKR register).
Bit 9 OIS1N: Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BKR register).
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BKR register).
Bit 7 Reserved, always read as 0.
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