STMicroelectronics STM32F05 series - Figure 97. Counter Timing Diagram, Internal Clock Divided by N; Figure 98. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)

RM0091 General-purpose timers (TIM2 and TIM3)
Doc ID 018940 Rev 1 297/742
Figure 97. Counter timing diagram, internal clock divided by N
Figure 98. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not
preloaded)
Timer clock = CK_CNT
Counter register
00
1F
20
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
CK_INT
00
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
01 02 03 04 05 06 0732 33 34 35 3631
Auto-reload register
FF 36
Write a new value in TIMx_ARR
CK_INT