Inter-integrated circuit (I
2
C) interface RM0091
488/742 Doc ID 018940 Rev 1
Figure 209. Master clock generation
Caution: In order to be I2C or SMBus compliant, the master clock must respect the timings given
below:
MS19858V1
t
SYNC1
SCL high level detected
SCLH counter starts
SCLH
SCL
SCL master clock generation
SCL released
SCL low level detected
SCLL counter starts
SCL driven low
SCLL
t
SYNC2
SCL master clock synchronization
SCLL
SCL driven low by
another device
SCL low level detected
SCLL counter starts
SCL released
SCLH
SCLH
SCL high level detected
SCLH counter starts
SCL high level detected
SCLH counter starts
SCL low level detected
SCLL counter starts
SCLL
SCL driven low by
another device
SCLH
SCL high level detected
SCLH counter starts
Table 66. I2C-SMBUS specification clock timings
Symbol Parameter
Standard Fast Mode
Fast Mode
Plus
SMBUS
Unit
Min Max Min Max Min Max Min Max
f
SCL
SCL clock frequency 100 400 1000 100 kHz
t
HD:STA
Hold time (repeated) START
condition
4.0 0.6 0.26 4.0 µs
t
SU:STA
Set-up time for a repeated START
condition
4.7 0.6 0.26 4.7 µs
t
SU:STO
Set-up time for STOP condition
4.0 0.6 0.26 4.0 µs
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