STMicroelectronics STM32F05 series - Figure 60. Counter Timing Diagram, Internal Clock Divided by N; Figure 61. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)

Advanced-control timers (TIM1) RM0091
234/742 Doc ID 018940 Rev 1
Figure 60. Counter timing diagram, internal clock divided by N
Figure 61. Counter timing diagram, update event with ARPE=1 (counter underflow)
Timer clock = CK_CNT
Counter register
00
20
1F
Update interrupt flag (UIF)
Counter underflow
Update event (UEV)
CK_PSC
01
CK_PSC
00
CEN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter underflow
Update event (UEV)
01 02 03 04 05 06 0705 04 03 02 0106
Auto-reload preload register
FD 36
Write a new value in TIMx_ARR
Auto-reload active register
FD 36