RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S)
Doc ID 018940 Rev 1 657/742
MSB justified standard
For this standard, the WS signal is generated at the same time as the first data bit, which is
the MSBit.
Figure 271. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0
Data are latched on the falling edge of CK (for transmitter) and are read on the rising edge
(for the receiver).
Figure 272. MSB justified 24-bit frame length with CPOL = 0
Figure 273. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0
MS30100 V1
CK
WS
SD
Transmission
Reception
16- or 32 bit data
MSB LSB
Channel left
Channel right
MSB
MS30101V1
CK
WS
SD
Transmission
Reception
24 bit data
MSB LSB
Channel left 32-bit
Channel right
8-bit remaining
0 forced
MS30102V1
CK
WS
SD
Transmission
Reception
16-bit data
MSB LSB
Channel left 32-bit
Channel right
16-bit remaining
0 forced
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