Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091
652/742 Doc ID 018940 Rev 1
Note: When the SPI is in slave mode, the CRC calculator is sensitive to the SCK slave input clock
as soon as the CRCEN bit is set, and this is the case whatever the value of the SPE bit. In
order to avoid any wrong CRC calculation, the software must enable CRC calculation only
when the clock is stable (in steady state). When the SPI interface is configured as a slave,
the NSS internal signal needs to be kept low between the data phase and the CRC phase.
26.5 SPI interrupts
During SPI communication an interrupts can be generated by the following events:
● Transmit TXFIFO ready to be loaded
● Data received in Receive RXFIFO
● Master mode fault
● Overrun error
● CRC error
● TI frame format error
Interrupts can be enabled and disabled separately.
26.6 I
2
S functional description
26.6.1 I
2
S general description
The block diagram of the I
2
S is shown in Figure 264.
Table 91. SPI interrupt requests
Interrupt event Event flag Enable Control bit
Transmit TXFIFO ready to be loaded TXE TXEIE
Data received in RXFIFO RXNE RXNEIE
Master Mode fault event MODF
ERRIE
Overrun error OVR
CRC error CRCERR
TI frame format error FRE
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