STMicroelectronics STM32F05 series User Manual

Option byte description RM0091
60/742 Doc ID 018940 Rev 1
Table 11. Description of the option bytes
Flash memory
address
Option bytes
0x1FFF F800
Bits [31:24] nUSER
Bits [23:16] USER: User option byte (stored in FLASH_OBR[15:8])
This byte is used to configure the following features:
– Select the watchdog event: Hardware or software.
– Reset event when entering Stop mode.
– Reset event when entering Standby mode.
Bit 23 : reserved
Bit 22 : RAM_PARITY_CHECK
0 : RAM parity check enabled
1 : RAM parity check disabled
Bit 21 : VDDA_MONITOR
0 : V
DDA
power supply supervisor disabled
1 : V
DDA
power supply supervisor enabled
Bit 20 : nBOOT1
Together with the BOOT0 pin, it selects the boot mode to the main Flash memory
SRAM or to the System memory.
Refer to Section 2.5: Boot configuration for more details.
Bit 19 : reserved
Bit 18: nRST_STDBY
0: Reset generated when entering Standby mode.
1: No reset generated.
Bit 17: nRST_STOP
0: Reset generated when entering Stop mode
1: No reset generated
Bit 16: WDG_SW
0: Hardware watchdog
1: Software watchdog
Bits [15:8]: nRDP
Bits [7:0]: RDP: Read protection option byte
The value of this byte defines the Flash memory protection level
0xAA : level 0 (ST production configuration)
0xXX (except 0xAA & 0xCC) : Level 1
0xCC : Level 2
Note : The protection level 1 and 2 are stored in the FLASH_OBR Flash option
register (RDPRT1 and RDPRT2 status flags respectively). Refer to Section 3.2.2:
Read operations for more details.
0x1FFF F804
Datax: Two bytes for user data storage.
These addresses can be programmed using the option byte programming
procedure.
Bits [31:24]: nData1
Bits [23:16]: Data1 (stored in FLASH_OBR[25:18])
Bits [15:8]: nData0
Bits [7:0]: Data0 (stored in FLASH_OBR[17:10])

STMicroelectronics STM32F05 series Specifications

General

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English