RM0091 Universal synchronous asynchronous receiver transmitter (USART)
Doc ID 018940 Rev 1 583/742
Tolerance of the USART receiver to clock deviation on page 587). In this case the
NF bit will never be set.
When noise is detected in a frame:
● The NF bit is set at the rising edge of the RXNE bit.
● The invalid data is transferred from the Shift register to the USART_RDR register.
● No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of
multibuffer communication an interrupt will be issued if the EIE bit is set in the
USART_CR3 register.
The NF bit is reset by setting NFCF bit in ICR register.
Note: Oversampling by 8 is not available in the Smartcard, IrDA and LIN modes. In those modes,
the OVER8 bit is forced to ‘0 by hardware.
Figure 233. Data sampling when oversampling by 16
Figure 234. Data sampling when oversampling by 8
Table 84. Noise detection from sampled data
Sampled value NE status Received bit value
000 0 0
001 1 0
010 1 0
011 1 1
100 1 0
101 1 1
RX LINE
Sample
clock
1234567891011
12
13 14 15 16
sampled values
One bit time
6/16
7/16
7/16
RX LINE
One bit time
3/8
3/8
12345678
2/8
Sample
clock(x8)
sampled values
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