Universal synchronous asynchronous receiver transmitter (USART) RM0091
582/742 Doc ID 018940 Rev 1
Selecting the clock source and the proper oversampling method
The choice of the clock source is done through the Clock Control system (see the Reset and
clock control (RCC) section). The clock source must be chosen before enabling the USART
(by setting the UE bit).
The choice of the clock source must be done according to two criteria:
● Possible use of the USART in low power mode
● Communication speed
The clock source frequency is f
CK
.
When the dual clock domain and the wakeup from Stop mode features are supported, the
clock source can be one of the following sources: f
PCLK
(default), f
LSE
, f
HSI
or f
SYS
.
Otherwise, the USART clock source is f
PCLK .
Choosing f
LSE
, f
HSI
as clock source may allow the USART to receive data while the MCU is
in low power mode. Depending on the received data and wakeup mode selection, the
USART wakes up the MCU, when needed, in order to transfer the received data by software
reading the USART_RDR register or by DMA.
For the other clock sources, the system must be active in order to allow USART
communication.
The communication speed range (specially the maximum communication speed) is also
determined by the clock source.
The receiver implements different user-configurable oversampling techniques (except in
synchronous mode) for data recovery by discriminating between valid incoming data and
noise. This allows a trade of between the maximum communication speed and noise/clock
inaccuracy immunity.
The oversampling method can be selected by programming the OVER8 bit in the
USART_CR1 register and can be either 16 or 8 times the baud rate clock (Figure 233 and
Figure 234).
Depending on the application:
● Select oversampling by 8 (OVER8=1) to achieve higher speed (up to f
CK
/8). In this case
the maximum receiver tolerance to clock deviation is reduced (refer to Section 25.5.5:
Tolerance of the USART receiver to clock deviation on page 587)
● Select oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to clock
deviations. In this case, the maximum speed is limited to maximum f
CK
/16
,where f
CK
is the clock source frequency.
Programming the ONEBIT bit in the USART_CR3 register selects the method used to
evaluate the logic level. There are two options:
● The majority vote of the three samples in the center of the received bit. In this case,
when the 3 samples used for the majority vote are not equal, the NF bit is set
● A single sample in the center of the received bit
Depending on the application:
– select the three samples’ majority vote method (ONEBIT=0) when operating in a
noisy environment and reject the data when a noise is detected (refer to Figure 84)
because this indicates that a glitch occurred during the sampling.
– select the single sample method (ONEBIT=1) when the line is noise-free to
increase the receiver’s tolerance to clock deviations (see Section 25.5.5:
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